1. Field of the Invention
The present invention relates to a redundancy circuit.
2. Description of the Background Art
FIGS. 7 and 8 illustrate a conventional redundancy circuit. Referring to FIG. 7, a memory cell array 24 comprising a plurality of memory cells 24a is connected with a 0-th bit line 3, a first bit line 4, . . . , a seventh bit line 10, and a spare bit line 11. A 0-th bit line selecting switch 12, a first bit line selecting switch 13, . . . , a seventh bit line selecting switch 19 and a spare bit line selecting switch 20 are provided successively in correspondence to the bit lines respectively.
The bit line selecting switches 12 to 20 are connected with a common bit line 25, to be further connected with an input/output control circuit 26 through the same. The bit lines 3 to 11 are successively provided with fuses 36 to 44 respectively.
The memory cell array 24 further comprises a row decoder 21, a row address input terminal 22 and word lines 23. A row address AXM which is formed by M data groups is inputted in the row address input terminal 22.
Referring to FIG. 8, a set of column addresses (Ay2, Ay1, Ay0) are inputted in column address input terminals 1, to be supplied to a column decoder 2 and a faulty line address generation circuit 45.
Faulty line address storage circuits 27a, 27b and 27c comprise fuses 28, 34 and 35 respectively. Since these faulty line address storage circuits 27a to 27c are similar in structure to each other, FIG. 8 illustrates only the internal structure of the faulty line address storage circuit 27a for the purpose of simplification. For example, the faulty line address storage circuit 27a comprises an inverter 29, a P-channel MOS transistor 30, a high resistor 31, a capacitor 32, and power supply terminals 33.
The faulty line address generation circuit 45 is connected with the faulty line address storage circuits 27a, 27b and 27c and a spare bit line selecting decoder 70.
The operation is now described. When combination of the column addresses is (Ay2, Ay1, Ay0)=(0, 0, 0), only an output QA0 is brought into a high level in the column decoder 2, to turn on only the 0-th bit line selecting switch 12 for selecting the 0-th bit line 3. When the combination of the column addresses is (Ay2, Ay1, Ay0)=(0, 0, 1), only an output QA1 is brought into a high level in the column decoder 2, to turn on only the first bit line selecting switch 13 for selecting the first bit line 4. When the combination of the column addresses is (Ay2, Ay1, Ay0)=(2, 1, 0), only an output QA2 is brought into a high level in the column decoder 2, to turn on only the second bit line selecting switch 14 for selecting the second bit line 5.
Thereafter in a similar manner, only an output QAK is brought into a high level in the column decoder 2 when the combination of the column addresses is at a value K (.ltoreq.7), to turn on only the K-th bit line selecting switch, thereby selecting the K-th bit line.
On the other hand, the row decoder 21 brings only one of the word lines 23, which corresponds to the row address AXM, into a high level. Among the memory cells 24a provided on the word line 23 which is thus brought into a high level, that provided on the bit line selected by the column decoder 2 is selected. Information of the memory cell 24a thus accessed through the row address AXM and the combination of the column addresses (Ay2, Ay1, Ay0) is written in or read out from the input/output control circuit 26 through the common bit line 25.
When the fuse 28 is not cut in the faulty line address storage circuit 27a, the output of the inverter 29 goes high, the P-channel MOS transistor 30 is turned off and an input of the inverter 29 stably goes low due to low impedance of the fuse 28. At this time, an output Fy0 of the faulty line address storage circuit 27a goes low.
When the fuse 28 is cut, on the other hand, the input potential of the inverter 29 is raised up by the high resistor 31, whereby the output of the inverter 29 goes low. The capacitor 32 reduces pullup impedance of the inverter 29 in a transient state such as a rise time of the power supply terminal 33, so that the output Fy0 of the faulty line address storage circuit 27a stably goes high.
When a faulty memory cell is provided on the 0-th bit line 3, the fuses 28, 34 and 35 are not cut in the faulty line address storage circuits 27a, 27b and 27c. Thus, outputs of the faulty line address storage circuits 27a, 27b and 27c are in combination of (Fy2, Fy1, Fy0)=(0, 0, 0).
These outputs Fy2, Fy1 and Fy0 are inputted in respective selector terminals S of selectors 45a, 45b and 45c forming the faulty line address generation circuit 45. The selectors 45a, 45b and 45c output signals supplied in input terminals A when values inputted in the selector terminals S are "1", while the same output inverted signals A* (hereinafter symbol * represents logic inversion) of those supplied in the input terminals A. In the aforementioned case, therefore, the faulty line address generation circuit 45 outputs Ay2*, Ay1* and Ay0*.
When a faulty memory cell is provided on the first bit line 4, the fuse 28 is cut so that (Fy2, Fy1, Fy0)=(0, 0, 1). At this time, the faulty line address generation circuit 45 outputs (Ay2*, Ay1*, Ay0).
This also applies to other faulty memory cells which are provided on other bit lines. When a faulty memory is provided on the second bit line 5, for example, the fuse 34 is cut so that (Fy2, Fy1, Fy0)=(0, 1, 0). At this time, the faulty line address generation circuit 45 outputs (Ay2*, Ay1, Ay0*).
The spare bit line selecting decoder 70 takes the logical product of the three outputs of the faulty line address generation circuit 45. Therefore, an output C of the spare bit line selecting decoder 70 becomes "1" only when the column addresses designate a bit line which is provided with a faulty memory cell.
When any one of the memory cells 24a provided on the fourth bit line 7 is faulty due to a process defect or the like, the fuse 40 is cut by a laser or the like. As to the faulty line address storage circuits 27a, 27b and 27c, the fuse 35 is cut so that the outputs are in combination of (Fy2, Fy1, Fy0)=(1, 0, 0) in correspondence to the fourth bit line 7.
When the column addresses are inputted in combination of (Ay2, Ay1, Ay0)=(1, 0, 0) corresponding to the faulty bit line, the output C of the spare bit line selecting decoder 70 takes a value "1", whereby the spare bit line selecting switch 20 is turned on to access a memory cell provided on the spare bit line 11.
On the other hand, information of the originally accessed memory cell which is provided on the fourth bit line 7 is completely cut off since the fourth bit line 7 is cut.
When a memory cell provided on any one of the 0-th to seventh bit lines is faulty, the bit line is replaced by the spare bit line 11, to remedy the fault of the memory cell array 24.
The conventional redundancy circuit has the aforementioned structure. When a storage circuit is contained in an ASIC (application specific IC) product, therefore, fuse coordinates must be inputted in a fuse cutter every product since fuse positions are varied with products depending on memory scales/structures, logical scales and memory arrangement coordinates.
While a storage circuit accesses memory cells in a disciplined manner with respect to supplied addresses, such access is irregularized after employment of a redundancy circuit and hence fault detectability of a fault detection pattern formed on the premise of discipline is disadvantageously reduced.